1. Technical Field
The present invention relates to a function test of a circuit (e.g., LSI), and more specifically to a circuit test pattern editing apparatus, circuit test pattern editing method, and signal-bearing medium embodying a program of circuit test pattern edition, for reducing the number of patterns of a test pattern used in a function test of the circuit (e.g., an LSI), and realizing a shorter clock cycle.
2. Background Art
With regard to a conventional test pattern for use in a function test of a circuit (e.g., an LSI), Japanese Patent Laid-Open No. 8-36032 describes an example of a conventional method of generating a test pattern for quickly performing a function test.
The conventional method of generating a delay/failure test pattern is an example of quickly generating a test pattern of an LSI, edits a test pattern by operating as described below, and compresses (reduces) the number of patterns.
That is, the conventional method of generating a delay/failure test pattern reads the number of patterns, input data, and clock signals for use in a function test in a period of test pattern.
Next, unless a clock signal and input data are simultaneously changed, it is determined that a pattern can be compressed, and the clock patterns expressed by “0”, “1”, and “0”, or three patterns of “0”, “1”, and “0” are defined as one pulse pattern of “P” or “N”.
Additionally, a test pattern is generated with the information that the pattern can be quickly processed set as speed information.
Then, a tester object for an LSI tester is generated from the test pattern as a delay/failure test pattern with the number of patterns reduced.